a current reference circuit is a basic building block in analog, digital and mixed-signal design systems. this work focuses on one type of integrated cmos current reference circuit. this source only uses one type of mosfet transistor and is suitable to produce very low currents in the order of nano amperes. despite being used in several works in the literature, there is no clear methodology to produce an optimal design for this source. with the absence of a design methodology, process variability becomes critical in affecting the performance of the current source. this variability issue is prominent in nanometer scaling of the technology. this work addresses that problem by developing a methodology to achieve a design with low area and low sensitivity to transistor mismatch. presented are the sensitivity and mismatch analysis, methodology, design example and results in addi- tion to performance figures for a lesser sensitive circuit as compared with its traditional counterpart. future scope of research has also been included in this thesis.