as transistor’s feature size shrinks, power becomes one of the limiting factors in design of modern processors. cache and register file are the two power hungry components in processors, consuming more than one third of total processors’ power budget. in this thesis, we propose new architectures for cache and register file to reduce power consumption. in the new architectures, we have sram cells operating at two different voltage levels and we change the structure of the cells so that they dynamically switch between nominal and reduced supply voltage. since power is proportional to voltage squared, an effective method to reduce power is lowering supply voltage. however, one of the side effects of using sram cells with reduced voltage is performance penalty. as supply voltage reduces, it takes longer to read/write from/to an sram cell. in this thesis, we exploit critical path instructions to overcome the performance impact of voltage scaling. critical path instructions are chain of dependent instructions that constrain speed of processors. those cells that are accessed frequently by critical instructions are assigned to use nominal supply voltage to preserve performance. on the other side, the cells that are seldom accessed by critical instructions are assigned to low supply voltage to reduce power consumption. to reduce overhead of voltage switching, we monitor critical instructions within long intervals and adjust the voltage of cells only when the intervals are elapsed. we have evaluated our optimization techniques using a combination of circuit and architectural simulators. first, we used hspice to measure both dynamic and static power and also latency of sram cells for nominal and reduced supply voltages. then, the results from hspice were fed into simplescalar for architectural evaluations. our simulation results reveal that the low power cache and register file reduce power consumption significantly with negligible impact on performance.